By Herman Casier, Michiel Steyaert, Arthur H.M. van Roermund
Analog Circuit layout relies at the every year Advances in Analog Circuit layout workshop. the purpose of the workshop is to collect designers of complex analogue and RF circuits for the aim of learning and discussing new percentages and destiny advancements during this box. chosen themes for AACD 2007 have been: (1) Sensors, Actuators and tool Drivers for the automobile and business surroundings; (2) built-in PA's from Wireline to RF; (3) Very excessive Frequency entrance Ends.
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Additional info for Analog Circuit Design: Sensors, Actuators and Power Drivers; Integrated Power Amplifiers from Wireline to RF; Very High Frequency Front Ends
Horsky A0 = - g m1 gm2 (9) The main limitation of this topology for gain A0¹1 is the transconductance dependency of the degenerated differential pair on the input voltage amplitude. By a slight modification of the described topology (Fig. 18) we can obtain a gain stage for which the input voltage seen by gm1 and gm2; for gm1= gm2 are equal even for A0¹1 and thus the transonductance dependences are canceled out. The topology is shown in Fig. 19. R1 G1 I1 + IN F2 _ G2 + 1 gm1 V F1 R2 I2 g m2 VOUT _ 1 R1 Fig.
Asides from the optical module, the most relevant analog design challenges for ACE chips, and in general for retina-like chips, are related to storage and to the realization of linear convolution operations with programmable kernels. In a linear convolution operation a kernel of weights is multiplied by each image spatial sample and its neighbourhood in a small region, the results summed, and the outcome used to change the sample . In the case of ACE and CACE chips two type of kernels per pixel are employed in accordance with the so-called CNN paradigm .
Driver realization The main challenges for the driver are a wide dynamic range of the output current and high speed (to limit losses the driver must be much faster than the oscillation frequency, which is typically 4MHz) . The wide dynamic range of the output current (0:1984) is obtained by a current DAC and parallel switching of Gm output stages in the driver. Since the relative resolution is limited, instead of using linear 11-bit DAC an exponential type 7-bit DAC has been used. The full 7-bit scale of the DAC is divided into 8 ranges and in each of these ranges the output current step is constant (piecewise linear approximation of exponential function) – see Fig.
Analog Circuit Design: Sensors, Actuators and Power Drivers; Integrated Power Amplifiers from Wireline to RF; Very High Frequency Front Ends by Herman Casier, Michiel Steyaert, Arthur H.M. van Roermund